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NLAS7242 High-Speed USB 2.0 (480 Mbps) DPDT Switches
The NLAS7242 is a DPDT switch optimized for high-speed USB 2.0 applications within portable systems. It features ultra-low on capacitance, CON = 7.5 pF (typ), and a bandwidth above 950 MHz. It is optimized for applications that use a single USB interface connector to route multiple signal types. The CON and RON of both channels are suitably low to allow the NLAS7242 to pass any speed USB data or audio signals going to a moderately resistive terminal such as an external headset. The device is offered in a UQFN10 1.4 mm x 1.8 mm package.
Features http://onsemi.com MARKING DIAGRAM
* * * * * * * * *
Optimized Flow-Through Pinout RON: 5.0 W Typ @ VCC = 4.2 V CON: 7.5 pF Typ @ VCC = 3.3 V VCC Range: 1.65 V to 4.5 V Typical Bandwidth: 950 MHz 1.4 mm x 1.8 mm x 0.50 mm UQFN10 OVT on Common Signal Pins D+/D- up to 5.25 V 8 kV HBM ESD Protection on All Pins This is a Pb-Free Device
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UQFN10 CASE 488AT
AD MG G
AD M G
= = =
Device Code Date Code Pb-Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device NLAS7242MUTBG Package UQFN0 (Pb-Free) Shipping 3000/Tape & Reel
Typical Applications
* High Speed USB 2.0 Data * Mobile Phones * Portable Devices
NLAS7242 HS USB XCVR
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
USB CONNECTOR
FS USB XCVR or AUDIO AMP
Figure 1. Application Diagram
(c) Semiconductor Components Industries, LLC, 2009
August, 2009 - Rev. 4
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Publication Order Number: NLAS7242/D
NLAS7242
HSD2+
7
HSD2-
6
OE VCC
8
5
HSD1+ HSD1- GND
9
4
CONTROL S
10 3
1
2
Figure 2. Pin Connections and Logic Diagram (Top View) Table 1. PIN DESCRIPTION
Pin S OE HSD1+, HSD1-, HSD2+, HSD2-, D+, D- Function Control Input Output Enable Data Ports OE 1 0 0 S X 0 1
D+
D-
Table 2. TRUTH TABLE
HSD1+, HSD1- OFF ON OFF HSD2+, HSD2- OFF OFF ON
MAXIMUM RATINGS
Symbol VCC VIS Pins VCC HSDn+, HSDn- D+, D- VIN ICC TS IIS_CON HSDn+, HSDn-, D+, D- HSDn+, HSDn-, D+, D- S, OE S, OE VCC Control Input Voltage, Output Enable Voltage Positive DC Supply Current Storage Temperature Analog Signal Continuous Current-Closed Switch Parameter Positive DC Supply Voltage Analog Signal Voltage Value -0.5 to +5.5 -0.5 to VCC + 0.3 -0.5 to +5.25 -0.5 to +5.5 50 -65 to +150 $300 V mA C mA Unit V V
IIS_PK
Analog Signal Continuous Current 10% Duty Cycle
$500
mA
IIN
Control Input Current, Output Enable Current
$20
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIS HSDn+, HSDn- D+, D- VIN TA S, OE Control Input Voltage, Output Enable Voltage Operating Temperature Pins Analog Signal Voltage Parameter Positive DC Supply Voltage Min 1.65 GND GND GND -40 Max 4.5 VCC 4.5 VCC +85 V C Unit V V
Minimum and maximum values are guaranteed through test or design across the Recommended Operating Conditions, where applicable. Typical values are listed for guidance only and are based on the particular conditions listed for section, where applicable. These conditions are valid for all values found in the characteristics tables unless otherwise specified in the test conditions.
ESD PROTECTION
Symbol ESD Human Body Model - All Pins Parameter Value 8.0 Unit kV
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NLAS7242
DC ELECTRICAL CHARACTERISTICS
CONTROL INPUT, OUTPUT ENABLE VOLTAGE (Typical: T = 25C)
-40C to +85C Symbol VIH Pins S, OE Parameter Control Input, Output Enable HIGH Voltage (See Figure 11) Control Input, Output Enable LOW Voltage (See Figure 11) Current Input, Output Enable Leakage Current 0 VIS VCC Test Conditions VCC (V) 2.7 3.3 4.2 2.7 3.3 4.2 1.65 - 4.5 Min 1.25 1.3 1.4 - Typ - Max - Unit V
VIL
S, OE
-
0.35 0.4 0.5 1.0
V
IIN
S, OE
-
-
mA
SUPPLY CURRENT AND LEAKAGE (Typical: T = 25C, VCC = 3.3 V)
-40C to +85C Symbol ICC IOZ IOFF D+, D- Pins VCC Parameter Quiescent Supply Current OFF State Leakage Power OFF Leakage Current Test Conditions 0 VIS VCC; ID = 0 A 0 VIS VCC - 0.5 V 0 VIS VCC 0 VIS VCC VCC (V) 1.65 - 3.6 3.6 - 4.5 1.65 - 4.5 0 Min - - - - Typ - - 0.1 - Max 1.0 1.0 1.0 1.0 Unit mA mA mA
LIMITED VIS SWING ON RESISTANCE (Typical: T = 25C)
-40C to +85C Symbol RON Pins Parameter On-Resistance (Note 1) Test Conditions ION = 8 mA VIS = 0 V to 0.4 V ION = 8 mA VIS = 0 V to 0.4 V ION = 8 mA VIS = 0 V to 0.4 V VCC (V) 2.7 3.3 4.2 2.7 3.3 4.2 2.7 3.3 4.2 Min - Typ 6.0 5.5 5.0 0.55 0.30 0.20 0.60 0.60 0.60 Max 8.6 7.6 7.0 - Unit W
RFLAT
On-Resistance Flatness (Notes 1 and 2) On-Resistance Matching (Notes 1 and 3)
-
W
DRON
-
-
W
1. Guaranteed by design. 2. Flatness is defined as the difference between the maximum and minimum value of On-Resistance as measured over the specified analog signal ranges. 3. DRON = RON(max) - RON(min) between HSD1+ and HSD1- or HSD2+ and HSD2-.
FULL VIS SWING ON RESISTANCE (Typical: T = 25C)
-40C to +85C Symbol RON Pins Parameter On-Resistance Test Conditions ION = 8 mA VIS = 0 V to VCC ION = 8 mA VIS = 0 V to VCC ION = 8 mA VIS = 0 V to VCC VCC (V) 2.7 3.3 4.2 2.7 3.3 4.2 2.7 3.3 4.2 Min - Typ 10 8.0 7.0 4.5 3.0 2.5 0.60 0.60 0.60 Max 13.5 9.75 8.50 - Unit W
RFLAT
On-Resistance Flatness (Notes 4 and 5) On-Resistance (Note 4 and 6)
-
W
DRON
-
-
W
4. Guaranteed by design. 5. Flatness is defined as the difference between the maximum and minimum value of On-Resistance as measured over the specified analog signal ranges. 6. DRON = RON(max) - RON(min) between HSD1+ and HSD1- or HSD2+ and HSD2-.
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NLAS7242
AC ELECTRICAL CHARACTERISTICS
TIMING/FREQUENCY (Typical: T = 25C, VCC = 3.3 V, RL = 50 W, CL = 35 pF, f = 1 MHz)
-405C to +855C Symbol tON tOFF TBBM BW Pins Closed to Open Open to Closed Parameter Turn-ON Time (See Figures 4 and 5) Turn-OFF Time (See Figures 4 and 5) Break-Before-Make Time (See Figure 3) -3 dB Bandwidth (See Figure 10) CL = 5 pF Test Conditions VCC (V) 1.65 - 4.5 1.65 - 4.5 1.65 - 4.5 1.65 - 4.5 Min - - 2.0 - Typ 13.0 12.0 - 950 Max 30.0 25.0 - - Unit ns ns ns MHz
ISOLATION (Typical: T = 25C, VCC = 3.3 V, RL = 50 W, CL = 5 pF)
-405C to +855C Symbol OIRR XTALK Pins Open HSDn+ to HSDn- Parameter OFF-Isolation (See Figure 6) Non-Adjacent Channel Crosstalk Test Conditions f = 240 MHz f = 240 MHz VCC (V) 1.65 - 4.5 1.65 - 4.5 Min - - Typ -22 -24 Max - - Unit dB dB
CAPACITANCE (Typical: T = 25C, VCC = 3.3 V, RL = 50 W, CL = 5 pF)
-405C to +855C Symbol CIN CON Pins S, OE D+ to HSD1+ or HSD2+ Parameter Control Pin, Output Enable Input Capacitance ON Capacitance Test Conditions VCC = 0 V, f = 1 MHz VCC = 0 V, f = 10 MHz VCC = 3.3 V; OE = 0 V, f = 1 MHz S = 0 V or 3.3 V VCC = 3.3 V; OE = 0 V, f = 10 MHz S = 0 V or 3.3 V OFF Capacitance VCC = VIS = 3.3 V; OE = 0 V, S = 3.3 V or 0 V, f = 1 MHz VCC = VIS = 3.3 V; OE = 0 V, S = 3.3 V or 0 V, f = 10 MHz Min - - - - - Typ 1.5 1.0 7.5 6.5 3.8 Max - - - - - Unit pF
COFF
HSD1n or HSD2n
-
2.0
-
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NLAS7242
DUT VCC 0.1 mF 50 W Output VOUT 35 pF Output Switch Select Pin 50 % OF DROOP Input GND tBMM VOLTAGE DROOP VCC
Figure 3. tBBM (Time Break-Before-Make)
VCC DUT VCC 0.1 mF Open Output VOUT 50 W 35 pF Output VOL Input tON tOFF Input 0V VOH 50% 50%
90%
90%
Figure 4. tON/tOFF
VCC DUT Output Open 50 W VOUT 35 pF Input
VCC 50% 0V VOH Output VOL 10% tOFF tON 10% 50%
Input
Figure 5. tON/tOFF
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NLAS7242
50 W Reference Input Output 50 W Generator 50 W DUT Transmitted
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. VISO = Off Channel Isolation = 20 Log VONL = On Channel Loss = 20 Log VOUT VIN for VIN at 100 kHz
VOUT for VIN at 100 kHz to 50 MHz VIN
Bandwidth (BW) = the frequency 3 dB below VONL VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50 W
Figure 6. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL
DETAILED DESCRIPTION
High Speed (480Mbps) USB 2.0 Optimized Over Voltage Tolerant
The NLAS7242 is a DPDT switch designed for USB applications within portable systems. The RON and CON of both switches are maintained at industry-leading low levels in order to ensure maximum signal integrity for USB 2.0 high speed data communication. The NLAS7242 switch can be used to switch between high speed (480Mbps) USB signals and a variety of audio or data signals such as full speed USB, UART or even a moderately resistive audio terminal.
The NLAS7242 features over voltage tolerant I/O protection on the common signal pins D+/D-. This allows the switch to interface directly with a USB connector. The D+/D- pins can withstand a short to VBUS, up to 5.25 V, continuous DC current for up to 24 hours as specified in the USB 2.0 specification. This protection is achieved without the need for any external resistors or protection devices.
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NLAS7242
NLAS7242
Figure 7. Board Schematic
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NLAS7242
Figure 8. Signal Quality
Figure 9. Near End Eye Diagram
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NLAS7242
Near End Test Data: Consecutive jitter range Std. Paired JK jitter range Paired KJ jitter range Consecutive jitter range N.C. Paired JK jitter range Paired KJ jitter range Consecutive jitter range N.O. Paired JK jitter range Paired KJ jitter range -54.37 -59.14 -50.79 -74.43 -61.60 -55.31 -82.55 -53.50 -62.60 73.21 59.56 34.57 81.65 58.55 48.43 80.33 71.65 47.30 ps ps ps ps ps ps ps ps ps -200 ps +200 ps -200 ps +200 ps -200 ps +200 ps Min Max
0 -0.5 -1 MAGNITUDE (dB) -1.5 -2 -2.5 -3 -3.5 -4 -4.5 1.0E+6 10.0E+6 100.0E+6 1.0E+9
FREQUENCY (Hz)
Figure 10. Magnitude vs. Frequency @ VCC = 3.3 V, All Temperatures ICC Leakage Current as a Function of VIN Voltage (255C)
2.50E-03 2.00E-03 1.50E-03 ICC 1.00E-03 5.00E-04 0.00E+00 -5.00E-04 4.2 V 3.3 V
2.7 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VIN (V)
Figure 11. ICC vs. VIN, Select Pin, All VCC's, 255C
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NLAS7242
PACKAGE DIMENSIONS
UQFN10 1.4x1.8, 0.4P CASE 488AT-01 ISSUE A
EDGE OF PACKAGE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D E e L L1 L3 MILLIMETERS MIN MAX 0.45 0.60 0.00 0.05 0.127 REF 0.15 0.25 1.40 BSC 1.80 BSC 0.40 BSC 0.30 0.50 0.00 0.15 0.40 0.60
D
A
PIN 1 REFERENCE 2X
0.10 C 0.10 C
2X
0.05 C 0.05 C
A A1 A1 SIDE VIEW
3 5 6 1
10X
C e/2 e
SEATING PLANE
9X
L
10
10 X
L3 BOTTOM VIEW
b
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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EE EE EE
EE EE
TOP VIEW
L1 E DETAIL A Bottom View (Optional)
EXPOSED Cu MOLD CMPD
B
A3
DETAIL B Side View (Optional)
MOUNTING FOOTPRINT*
1.700 0.0669 0.663 0.0261 0.200 0.0079 0.563 0.0221
9X
1
2.100 0.0827 0.400 0.0157 PITCH
0.225 0.0089
10 X
SCALE 20:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
NLAS7242/D

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